[hercules-os380] GCC on MVS/380 0C4 for 31 bit storage

[Amrith [e-mail] [hercules-os380]]

Paul/List,         I have been consistently getting 0C4 when I run GCC on MVS380. I see that for large compilations GCC tries to acquire storage above the line and goes down with 0C4. I checked if SVC120I was active and the MVS/380 code for the intercept was used and Not the IBM  one. I then decided to write a small code to acquire 30MB of storage and it went down with 0C4 as well. When I switched to Supervised state with inline assembly in C using MODESET and in KEY ZERO the 30MB of storage was acquired. I did print the address and also tried writing to the storage and all was well. The problem is that while running GCC as a job step for compilations which requires ATL memory I still get the 0C4.
I am on Windows 7 with hercules-3.07:380 4.x, MVS/380.
Any idea what needs to be done?

Thanks,Amrith

[[e-mail] [hercules-os380]]

Hi Amrith.

Are you using the latest mvs380 and gccmvs beta and doing a fresh ipl? Can you get a dump and post the rtm2wa info?

Paul

[Amrith [e-mail] [hercules-os380]]

Subject: Re: GCC on MVS/380 0C4 for 31 bit storage
Date: Sunday, August 12, 2018, 2:45 PM
Program
#include
<stdio.h>                
 
#include
<string.h>               
 
#include
<stdlib.h>               
 
int
main(void)                    
 
{                                 
 
   
void
*ptr;                    
 
   
ptr=(void *)malloc(30000000);   
   
return
(0);                   
 
}                                 
 
                             
RTM2WA
SUMMARY                                  
 
                             
--------------                                  
 
                                                                              
 
+1C    
COMPLETION
CODE         
800C4000                                     
 
+8C    
ABENDING PROGRAM NAME     
N/A                                        
 
+94    
ABENDING PROGRAM ADDR   
00000000                                     
 
                                                                              
 
+3C    
REGS AT TIME OF ERROR    01C9C3C0 02001000
000A73B0 01C9C3C0 01C9C380 00000000 000B4062
00000000   (0-7)
+5C                             
00000000 000A74A0 000A5EE8 000B41F0 000A8F42 400A5ED0
00000000   (8-F)  
+7C    
EC PSW AT TIME OF ERROR  078D0000 000A8F7E 00040004
00114800          
 
+DC    
SDWACOMP                
00000000                                     
 
                                                                              
 
+E8    
RETURN CODE FROM RECOVERY ROUTINE-00,CONTINUE WITH
TERMINATION-IMPLIES PERCOLATION   
+E0    
RETRY ADDR RETURNED FROM RECOVERY EXIT 
00000000                      
 
+E4    
RB ADDR FOR
RETRY                      
00000000                      
 
                                                                              
 
+C     
CVT 
ADDR                  
00017860                                  
 
+38    
RTCT
ADDR                  
00FD4128                                  
 
+C8    
SCB 
ADDR                  
00000001                                  
 
+D4    
SDWA
ADDR                  
00000000                                  
 
+14    
SVRB
ADDR                  
009BE5F0                                  
 
SAVE
AREA
TRACE                                                      
 
PDPTEST 
WAS ENTERED VIA
LINK         AT EP
@@CRT0                   
 
SA  
0A4FB0  WD1 00000000   HSA
00000000   LSA 000B3ED0   RET 000178B0
EPA 000A5D50   R0  009BE508
            
R1  000A4FF8   R2  00000040  
R3  009B0634   R4  009B0610 R5 
009BC7B0   R6  00986018  
            
R7  FD000000   R8  009BC020  
R9  809BC710   R10 00000000 R11
00000000   R12 40E94B9A  
PDPTEST 
WAS ENTERED VIA
CALL         AT EP
@@START                  
 
SA  
0B3ED0  WD1 00000000   HSA
000A4FB0   LSA 000B4000   RET 500A5E0A
EPA 000A74D0   R0  00040130
            
R1  000B3F20   R2  000B3F2C  
R3  00040000   R4  009B0610 R5 
000B3ED0   R6  00986018
            
R7  009BC118   R8  0099A000  
R9  809BC710   R10 000A5D50 R11
000A4FF8   R12 000B3F38
PDPTEST 
WAS ENTERED VIA
CALL         AT EP
MAIN                     
 
SA  
0B4000  WD1 00000000   HSA
000B3ED0   LSA 000B4198   RET 400A7912
EPA 000A5CE4   R0  00040130
            
R1  000B4058   R2  000A73B0  
R3  00000001   R4  000000FD R5 
00000000   R6  000B4062   
            
R7  00000000   R8  00000000  
R9  000A74A0   R10 000A79C0 R11
000B3F20   R12 500A7502   
PDPTEST 
WAS ENTERED VIA
CALL         AT EP
MALLOC                   
 
SA  
0B4198  WD1 00000000   HSA
000B4000   LSA 000B41F8   RET 400A5D28
EPA 000A5E88   R0  00040130   
 
            
R1  000B41F0   R2  000A73B0  
R3  00000001   R4  000000FD R5 
00000000   R6  000B4062
            
R7  00000000   R8  00000000  
R9  000A74A0   R10 000A5D44 R11
000B4058   R12 400A5D12
PDPTEST 
WAS ENTERED VIA
CALL         AT EP
@@GETM                   
 
SA  
0B41F8  WD1 00000000   HSA
000B4198   LSA 000B4258   RET 400A5ED0
EPA 000A8F42   R0  00040130
            
R1  000B4250   R2  000A73B0  
R3  00000001   R4  000000FD R5 
00000000   R6  000B4062  
            
R7  00000000   R8  00000000  
R9  000A74A0   R10 000A5EE8 R11
000B41F0   R12 400A5EBA
PDPTEST 
WAS ENTERED VIA
CALL         AT EP
MALLOC                            
 
SA  
0B4258  WD1 00000000   HSA
000B41F8   LSA 000B42B8   RET
400AB8E8   EPA 000A5E88   R0 
00040130
            
R1  000B42B0   R2  000F4110  
R3  00000008   R4  000B2B30  
R5  000B2B30   R6  000F4110
            
R7  009BC118   R8  0099A000  
R9  000A4FFE   R10 000ABAC4   R11
000B4250   R12 400AB8CA
PDPTEST 
WAS ENTERED VIA
CALL         AT EP
@@GETM                            
 
SA  
0B42B8  WD1 000F4118   HSA
000B4258   LSA 000F4124   RET
400A5ED0   EPA 000A8F42   R0 
00040130
            
R1  000B4310   R2  000F4110  
R3  00000008   R4  000B2B30  
R5  000B2B30   R6  000F4110
            
R7  009BC118   R8  0099A000  
R9  000A4FFE   R10 000A5EE8   R11
000B42B0   R12 400A5EBA
INVALID
BACK
CHAIN                                                            
 
SA  
0F4124  WD1 00001859   HSA
E2E8E2C9   LSA D5404040   RET
00000000   EPA 00000000   R0 
00000000
            
R1  00000000   R2  00000000  
R3  00000000   R4  00000000  
R5  00000000   R6  00000001
            
R7  00000001   R8  00000002  
R9  00000000   R10 0010CFCC   R11
000000FB   R12 0010CFCC
INTERRUPT
AT
0A8F7E                                                           
 

[[e-mail] [hercules-os380]]

Hi Amrith.

My reading of the psw is that you were running as am24 at the time of error.

Modern gcc beta requires modern iewl to set am31 and requires modern mvs380 to honor the am31 flag.

However, even running am24 i do expect an out of memory error rather than a s0c4.

I think what is happening is that you are using the old svc120i instead of mvs380mn and it returns an atl address which is then interpreted as a 24 bit address. Modern mvs380mn should not have that problem.

Paul

[[e-mail] [hercules-os380]]

Another thing to note - when you install mvs380-beta5 you only need mvs380mn in sys2.linklib (or sys1) and mvs380ft in sys1.lpalib plus a proc to execute mvs380mn with parm example of add,numpart=2 (from memory).

Paul

[[e-mail] [hercules-os380]]

Regarding the s878 email which i cant reply to at the moment. Do a fresh ipl and check what partition size mvs380mn reports

Paul

[[e-mail] [hercules-os380]]

ptr=(void *)malloc(30000000);
RTM2WA
REGS AT TIME OF ERROR 01C9C3C0 02001000

R0 is showing a length of approx 30 MB,
and R1 is showing a correct ATL address.

MVS380MN is only supposed to be returning
an ATL address when the application is
running as AM31.

I suspect you are not actually running the
new MVS380MN code, you are instead
running the old MVS/380 which would
unconditionally return an ATL address
if given a large size.

So you upgraded to the new GCC but not
the new MVS/380. The new GCC produces
modules that will not force themselves into
AM31, they will instead just be marked as
AM31 by the new IEWL and then they rely
on MVS/380 (module MVS380FT) to activate
AM31.

BFN. Paul.

[[e-mail] [hercules-os380]]

Post by ***@yahoo.com.au [hercules-os380]

REGS AT TIME OF ERROR 01C9C3C0 02001000

R0 is showing a length of approx 30 MB,
and R1 is showing a correct ATL address.

And since you are running as AM24, that
returned address will be treated as
address x'1000' which is low memory and
I don't know what happens if you try to
write to low memory, but it won't be good.
You'll get a S0C4 if you do it in problem
mode, and in supervisor mode, who knows.

BFN. Paul.

[[e-mail] [hercules-os380]]

Post by ***@yahoo.com.au [hercules-os380]
The new GCC produces
modules that will not force themselves into
AM31, they will instead just be marked as
AM31 by the new IEWL and then they rely
on MVS/380 (module MVS380FT) to activate
AM31.

Note that the old versions of MVS/380
that did not honor the AM31 bit, and nor
did they allow multiple ATL requests, are
being treated as junk betas and load
modules like GCC do not cater to them.
Instead, MVS/XA or MVS/380 2.0 (which
is what those betas I uploaded are), are
the minimum requirements for 31-bit
support for any module I produce.

BFN. Paul.